MC68HC908LB8_05 Datasheet, PDF (153/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Control Logic Block
Clearing the PWMEN bit before entering wait mode will reduce power consumption in wait mode because
the counter, prescaler divider, and LDFQ divider will no longer be clocked. In addition, power will be
reduced because the PWMs will no longer toggle.
15.7.2 Stop Mode
When the microcontroller is put into stop mode via the STOP instruction, the PWM will stop functioning.
The PWM0 and PWM1 outputs are set to logic 0. The STOP instruction does not affect the register
conditions or the state of the PWM counters. When the MCU exits stop mode after an external interrupt
the PWM resumes operation.
15.8 Control Logic Block
This subsection provides a description of the control logic block.
15.8.1 PWM Counter Registers
The PWM counter registers (PCNTH and PCNTL) display the 12-bit up-only counter. When the high byte
of the counter is read, the lower byte is latched. PCNTL will hold this latched value until it is read. See
Figure 15-14 and
Figure 15-15.
Address:
Read:
Write:
Reset:
$0045
Bit 7
0
0
6
5
0
0
0
0
= Unimplemented
4
3
2
1
Bit 0
0
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
Figure 15-14. PWM Counter Register High (PCNTH)
Address: $0046
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-15. PWM Counter Register Low (PCNTL)
15.8.2 PWM Counter Modulo Registers
The PWM counter modulus registers (PMODH and PMODL) hold a 12-bit unsigned number that
determines the maximum count for the up-only counter. The PWM period will equal the modulus. See
Figure 15-16 and Figure 15-17.
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
153