MC68HC908LB8_05 Datasheet, PDF (50/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Analog-to-Digital Converter (ADC)
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be unknown or re-
served.
2. V_REFH and V_REFL are internally connected to V_DD and V_SS respectively.
3.8.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address: $003E
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 3-4. ADC Data Register (ADR)
3.8.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
ADIV2 ADIV1 ADIV0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-5. ADC Clock Register (ADCLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal
ADC clock. Table 3-2 shows the available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Table 3-2. ADC Clock Divide Ratio
ADIV2
ADIV1
0
0
0
0
0
1
0
1
1
X⁽¹⁾
NOTES:
1. X = Don’t care
ADIV0
0
1
0
1
X⁽¹⁾
ADC Clock Rate
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
MC68HC908LB8 Data Sheet, Rev. 1
50
Freescale Semiconductor