MC68HC908LB8_05 Datasheet, PDF (160/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Pulse Width Modulator with Fault Input (PWM)
15.8.9 Fault Control Register 2
The fault control register 2 (FCR2) is used to acknowledge and clear the FFLAG.
Address: $0044
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
0
Write:
FTACK
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-25. Fault Control Register (FCR2)
FTACK — Fault Acknowledge Bit
The FTACK bit is used to acknowledge and clear FFLAG. This bit will always read 0. Writing a 1 to this
bit will clear FFLAG. Writing a 0 will have no effect.
15.9 PWM Glossary
CPU cycle
One internal bus cycle (1/BUSCLK)
PWM clock cycle (or period)
One tick of the PWM counter (1/BUSCLK with no prescaler). See Figure 15-26.
PWM cycle (or period)
Edge-aligned mode: The time it takes the PWM counter to count up (modulus/BUSCLK). See
Figure 15-26.
Edge-Aligned Mode
PWM
CLOCK
CYCLE
PWM CYCLE (OR PERIOD)
Figure 15-26. PWM Clock Cycle and PWM Cycle Definition
MC68HC908LB8 Data Sheet, Rev. 1
160
Freescale Semiconductor