MC68HC908LB8_05 Datasheet, PDF (108/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

High Resolution PWM (HRP)
Read:
Write:
P2
P1
P0
STEP4 STEP3 STEP2 STEP1 STEP0
Reset:
0
0
0
0
0
0
0
0
Figure 10-12. HRP Period Registers (HRPPERH:HRPPERL)
P[10:0] — 11-Bit Period Value
STEP[4:0] — 5-Bit Dithering Step Value
10.8.4 HRP Deadtime Register
This read/write register contains an 8-bit value corresponding to the number of HRPCLK cycles that will
be subtracted from the logic 1 level of the TOP and BOT output signals to provide deadtime between the
two signals.
Dead Time = ---H-----R----P----D----T-----
HRPCLK
(EQ 10-14)
Address: $0056
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write: ^DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Reset:
0
0
0
0
1
0
0
0
Figure 10-13. HRP Deadtime Register (HRPDT)
10.8.5 Frequency Dithering HRP Timebase Registers
The two read/write frequency dithering timebase registers HRPTBH:HRPTBL contain a 16-bit value used
to determine the time base for switching between the two dithering frequencies. The timebase is
calculated from the following formula:
Frequency Dithering Timebase (seconds) = ^{H-----R----P----T----B----H----:--H----R-----P----T---B----L--}
HRPCLK
(EQ 10-15)
Writes to the high byte (HRPTBH) are stored in a latch until the low byte (HRPTBL) is written. Both
registers are then updated simultaneously. This prevents glitches occurring on the output signal.
Address: HRPTBH — $0057 HRPTBL — $0058
Bit 15
14
13
12
11
10
9
Bit 8
Read:
TB15
TB14
TB13
TB12
TB11
TB10
TB9
TB8
Write:
Reset:
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 10-14. HRP Timebase Registers (HRPTBH:HRPTBL)
MC68HC908LB8 Data Sheet, Rev. 1
108
Freescale Semiconductor