MC68HC908LB8_05 Datasheet, PDF (106/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

High Resolution PWM (HRP)
This read/write bit enables the SHTDWN functionality on pin PTC2/SHTDWN/IRQ. When SHTDWN
functionality is enabled, a falling edge or a low level on the SHTDWN pin causes the TOP and BOT
outputs to be switched to logic 0 and the HRPEN bit is set to logic 0, disabling the HRP.
1 = Pin PTC2/SHTDWN/IRQ functions as SHTDWN input.
0 = Pin PTC2/SHTDWN/IRQ functions controlled by port C register
NOTE
The TOP and BOT pins must be enabled using the HRPOE bit for the
HRPEN bit to have any effect on the PTB0/TOP and PTB1/BOT I/O pins.
HRPMODE — Mode Select
This read/write bit selects between variable frequency and variable duty cycle modes of operation.
1 = Variable duty cycle mode
0 = Variable frequency mode
HRPEN — Enable
This read/write bit enables/disables the HRP.
1 = HRP enabled
0 = HRP disabled
When the HRP is disabled the TOP and BOT outputs both switch to logic 0. If a logic 0 is detected on the
SHTDWN input pin, the module outputs both switch to logic 0 and the HRPEN bit is automatically set to 0
to disable the module.
NOTE
The TOP and BOT pins must be enabled using the HRPOE bit for the
HRPEN bit to have any effect on the PTB0/TOP and PTB1/BOT I/O pins.
10.8.2 HRP Duty Cycle Registers
The two read/write duty cycle registers contain the 16-bit duty cycle of the output after dithering. It is split
into two parts:
1. 11-bit duty cycle value (DC[10:0]) used to generate the HRP output waveforms.
2. 5-bit step value (STEP[4:0]) that defines the percentage of time spent on the larger of two duty
cycle values in variable duty cycle mode.
The duty cycle including dithering in variable duty cycle mode is:
Output Duty Cycle = ^{D-----C-----[}--1----0---:--0----^] + ---I--N-----T----^⎝⎛----S--------T2------E--^{S------EP----L------[[--2}--4--^:--^{0--:----]0--------]}--^⎠⎞----
HRPCLK _{-------3---2--------- ¥ HRPCLK}
2^SEL[2:0]
where 2^SEL[2:0] is the STEP[4:0] scaling factor.
(EQ 10-11)
HRPDCH:HRPDCL are not used in variable frequency mode. The contents of the registers have no effect
in this mode
Writes to the high byte (HRPDCH) are stored in a latch until the low byte (HRPDCL) is written. Both
registers are then updated simultaneously. This prevents glitches in the output duty cycle.
MC68HC908LB8 Data Sheet, Rev. 1
106
Freescale Semiconductor