MC68HC908LB8_05 Datasheet, PDF (175/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Reset and System Initialization
See Figure 17-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI,
or POR. See Figure 17-6.
NOTE
For LVI or POR resets, the SIM cycles through 4096 + 32 BUSCLKX4
cycles during which the SIM forces the RST pin low. The internal reset
signal then follows the sequence from the falling edge of RST shown in
Figure 17-5.
IRST
RST
BUSCLKX4
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
IAB
Figure 17-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
VECTOR HIGH
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
MODRST
INTERNAL RESET
Figure 17-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
17.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 BUSCLKX4 cycles. Thirty-two BUSCLKX4 cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
At power-on, these events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables the oscillator to drive BUSCLKX4.
• Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKX4 cycles to allow
stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
175