MC68HC908LB8_05 Datasheet, PDF (173/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

SIM Bus Clock Control and Generation
Addr. Register Name
Bit 7
6
5
4
3
2
1
$FE00
Break Status Register ^Read:
R
(BSR) Write:
R
R
R
R
SBSW
R
Note⁽¹⁾
See page 183. _Reset:
0
0
0
0
0
0
0
1. Writing a 0 clears SBSW.
$FE01
$FE03
SIM Reset Status
Register (SRSR)
See page 184.
Read:
Write:
POR:
Break Flag Control Register ^Read:
(BFCR) Write:
See page 185. _Reset:
POR
1
BCFE
0
PIN
COP
0
0
R
R
= Unimplemented
ILOP
ILAD MODRST LVI
0
0
0
0
R
R
R
R
R
= Reserved
Figure 17-2. SIM I/O Register Summary
Bit 0
R
0
0
0
R
17.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, BUSCLKX2, as shown in Figure 17-3.
FROM
OSCILLATOR
FROM
OSCILLATOR
BUSCLKX4
BUSCLKX2
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Figure 17-3. SIM Clock Signals
17.2.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four.
17.2.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed. The
RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the
time out.
17.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows BUSCLKX4 to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay time out. This time out is
selectable as 4096 or 32 BUSCLKX4 cycles. See 17.6.2 Stop Mode.
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
173