MC68HC908LB8_05 Datasheet, PDF (82/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

External Interrupt (IRQ)
IRQPUD
ACK
RESET
VECTOR
FETCH
DECODER
V_DD
INTERNAL
PULLUP
DEVICE
IRQ
V_DD
D ^CLR Q
CK
IRQ
FF
SYNCHRO-
NIZER
IMASK
IRQF
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ
INTERRUPT
REQUEST
MODE
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 8-1. IRQ Module Block Diagram
When an interrupt pin is both falling-edge and low-level triggered, the interrupt remains set until both of
these events occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR masks all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
Addr.
$001D
Register Name
Bit 7
6
5
IRQ Status and Control ^Read:
0
0
0
Register (INTSCR) Write:
See page 84. _Reset:
0
0
0
= Unimplemented
4
3
2
1
Bit 0
0
IRQF
0
IMASK MODE
ACK
0
0
0
0
0
Figure 8-2. IRQ I/O Register Summary
8.4 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear,
or reset clears the IRQ latch.
MC68HC908LB8 Data Sheet, Rev. 1
82
Freescale Semiconductor