MC68HC908LB8_05 Datasheet, PDF (178/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

System Integration Module (SIM)
MODULE
INTERRUPT
I BIT
IAB
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4 VECT H VECT L START ADDR
IDB
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
R/W
Figure 17-8. Interrupt Entry Timing
MODULE
INTERRUPT
I BIT
IAB
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
IDB
CCR
A
X
PC – 1 [7:0] PC – 1 [15:8] OPCODE OPERAND
R/W
Figure 17-9. Interrupt Recovery Timing
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). See Figure 17-10.
17.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 17-11 demonstrates what happens when two interrupts are pending. If an interrupt
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
MC68HC908LB8 Data Sheet, Rev. 1
178
Freescale Semiconductor