MC68HC908LB8_05 Datasheet, PDF (114/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Low-Power Modes
11.3.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register
states.
11.4 Central Processor Unit (CPU)
11.4.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
11.4.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
11.5 Computer Operating Properly Module (COP)
11.5.1 Wait Mode
The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout.
11.5.2 Stop Mode
Stop mode turns off the COPCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
The STOP bit in the CONFIG1 register enables the STOP instruction. To prevent inadvertently turning off
the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit.
11.6 External Interrupt Module (IRQ)
11.6.1 Wait Mode
The external interrupt (IRQ) module remains active in wait mode. Clearing the IMASK bit in the IRQ status
and control register enables IRQ CPU interrupt requests to bring the MCU out of wait mode if IRQ function
is enabled.
11.6.2 Stop Mode
The IRQ module remains active in stop mode. Clearing the IMASK bit in the IRQ status and control
register enables IRQ CPU interrupt requests to bring the MCU out of stop mode.
MC68HC908LB8 Data Sheet, Rev. 1
114
Freescale Semiconductor