MC68HC908LB8_05 Datasheet, PDF (183/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note: Previous data can be operand data or the STOP opcode, depending
on the last instruction.
Figure 17-15. Stop Mode Entry Timing
SIM Registers
BUSCLKX4
STOP RECOVERY PERIOD
INT/BREAK
IAB
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 17-16. Stop Mode Recovery from Interrupt
17.7 SIM Registers
The SIM has three memory-mapped registers. Table 17-3 shows the mapping of these registers.
Table 17-3. SIM Registers
Address
$FE00
$FE01
$FE03
Register
BSR
SRSR
BFCR
Access Mode
User
User
User
17.7.1 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
Write:
R
R
R
R
R
Note⁽¹⁾
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
1. Writing a 0 clears SBSW.
Figure 17-17. Break Status Register (BSR)
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
183