MC68HC908LB8_05 Datasheet, PDF (96/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

High Resolution PWM (HRP)
PERIOD +1 = $81
FREQUENCY = 1/ ($81 * 125 ns) = 62.015 kHz
PERIOD = $80
t
FREQUENCY = 1/ ($80 * 125 ns) = 62.500 kHz
PERIOD +1 = $81
PERIOD = $80
STEPS
0
8
16
24
0
8
16
24
0
AVERAGE FREQUENCY = 62.015 + ((62.500 – 62.015)/32 * 8) = 62.136 kHz
Figure 10-5. High Resolution PWM Dithering
10.4.3 Duty Cycle Dithering
As an alternative to frequency dithering, duty cycle dithering, where dithering occurs between two signals
having the same frequency, but with duty cycles differing by one clock period. The HRP can perform duty
cycle dithering with the same step resolution as the frequency dithering option (125/32 = 3.906 ns, with
an 8 MHz clock).
10.4.4 Frequency Generation
The dual frequency generator block contains a 16-bit up counter, which generates an output signal, based
on the values in the period register HRPPERH:HRPPERL and the duty cycle register HRPDCH:HRPDCL.
The output signal and its inverse are later fed into the deadtime generators for deadtime insertion.
Multiplexors on the inputs of the period register and the duty cycle register select between two period
(PERIOD1 and PERIOD2) and two duty cycle (DUTY1 and DUTY2) values. The values of PERIOD1,
PERIOD2, DUTY1, and DUTY2 are determined by the HRPMODE bit in the HRPCTRL register and the
contents of the HRPPERH:HRPPERL and HRPDCH:HRPDCL registers.
PERIOD1 and DUTY1 define the frequency output by the dual-frequency generator; PERIOD2 and
DUTY2 define a second output frequency, which is automatically calculated by the HRP module.
The module switches between PERIOD1/DUTY1 and PERIOD2/DUTY2.
MC68HC908LB8 Data Sheet, Rev. 1
96
Freescale Semiconductor