MC68HC908LB8_05 Datasheet, PDF (196/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Timer Interface Module (TIM)
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as
Table 18-1 shows. Reset clears the PS[2:0] bits.
Table 18-1. Prescaler Selection
PS2
PS1
PS0
TIM Clock Source
0
0
0
Internal bus clock ÷ 1
0
0
1
Internal bus clock ÷ 2
0
1
0
Internal bus clock ÷ 4
0
1
1
Internal bus clock ÷ 8
1
0
0
Internal bus clock ÷ 16
1
0
1
Internal bus clock ÷ 32
1
1
0
Internal bus clock ÷ 64
1
1
1
Not available
18.8.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
Address: $0021
Bit 7
6
5
4
3
2
Read: Bit 15
14
13
12
11
10
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
1
Bit 0
9
Bit 8
0
0
Figure 18-6. TIM Counter Registers High (TCNTH)
Address: $0022
Figure 18-7. TIM Counter Registers Low (TCNTL)
MC68HC908LB8 Data Sheet, Rev. 1
196
Freescale Semiconductor