MC68HC908LB8_05 Datasheet, PDF (201/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

I/O Registers
18.8.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: $0026
Bit 7
6
Read: _{Bit 15}
14
Write:
Reset:
5
4
3
2
13
12
11
10
Indeterminate after reset
1
Bit 0
9
Bit 8
Figure 18-13. TIM Channel 0 Register High (TCH0H)
Address: $0027
Bit 7
6
Read:
Write:
Bit 7
6
Reset:
5
4
3
2
5
4
3
2
Indeterminate after reset
1
Bit 0
1
Bit 0
Figure 18-14. TIM Channel 0 Register Low (TCH0L)
Address: $0029
Bit 7
6
Read:
Write: ^{Bit 15}
14
Reset:
5
4
3
2
13
12
11
10
Indeterminate after reset
1
Bit 0
9
Bit 8
Figure 18-15. TIM Channel 1 Register High (TCH1H)
Address: $002A
Bit 7
6
Read: _{Bit 7}
6
Write:
Reset:
5
4
3
2
5
4
3
2
Indeterminate after reset
1
Bit 0
1
Bit 0
Figure 18-16. TIM Channel 1 Register Low (TCH1L)
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
201