MC68HC908LB8_05 Datasheet, PDF (157/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Control Logic Block
Address: $0041
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LDFQ1 LDFQ0
DIS1
DIS0
POL1
POL0 PRSC1 PRSC0
Write:
Reset:
0
0
0
0
1
1
0
0
Bold = Buffered
Figure 15-21. PWM Control Register 2 (PCTL2)
LDFQ1 and LDFQ0 — PWM Load Frequency Bits
These buffered read/write bits select the PWM CPU load frequency according to Table 15-4.
NOTE
When reading these bits, the value read is the buffer value (not necessarily
the value the PWM generator is currently using).
The LDFQx bits take effect when the current load cycle is complete
regardless of the state of the load okay bit, LDOK.
Table 15-4. PWM Reload Frequency
Reload Frequency Bits
LDFQ1 and LDFQ0
00
01
10
11
PWM Reload
Frequency
Every PWM cycle
Every 2 PWM cycles
Every 4 PWM cycles
Every 8 PWM cycles
NOTE
Reading the LDFQx bit reads the buffered values and not necessarily the
values currently in effect.
DIS1 — Software Disable Bit for PWM1
This read/write bit allows the user to disable pin PWM1.
1 = Disable PWM1
0 = Re-enable PWM1
DIS0 — Software Disable Bit for PWM0
This read/write bit allows the user to disable pin PWM0.
1 = Disable PWM0
0 = Re-enable PWM0
POL1 — Polarity Bit for PWM1
This read/write bit selects the polarity of the PWM waveform of PWM1. Positive polarity means that
when the PWM is active the PWM output is high. Conversely, negative polarity means that when the
PWM is active the PWM output is low.
1 = PWM1 has positive polarity
0 = PWM1 has negative polarity
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
157