MC68HC908LB8_05 Datasheet, PDF (133/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Chapter 14
Input/Output (I/O) Ports
14.1 Introduction
Bidirectional input-output (I/O) pins form three parallel ports. All I/O pins are programmable as inputs or
outputs. All individual bits within port A and port C are software configurable with pullup devices if
configured as input port bits. The pullup devices are automatically and dynamically disabled when a port
bit is switched to output mode.
NOTE
Connect any unused I/O pins to an appropriate logic level, either V_DD or
V_SS. Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Addr.
$0000
$0001
$0002
$0004
$0005
$0006
Register Name
Port A Data Register ^Read:
(PTA) Write:
See page 134. _Reset:
Port B Data Register ^Read:
(PTB) Write:
See page 136. _Reset:
Port C Data Register ^Read:
(PTC) Write:
See page 138. _Reset:
Data Direction Register A ^Read:
(DDRA) Write:
See page 135. _Reset:
Data Direction Register B ^Read:
(DDRB) Write:
See page 137. _Reset:
Data Direction Register C ^Read:
(DDRC) Write:
See page 139. _Reset:
Bit 7
0
PTB7
0
0
0
0
DDRB7
0
0
0
6
PTA6
5
PTA5
PTB6
PTB5
0
0
0
DDRA6
0
DDRB6
0
0
0
DDRA5
0
DDRB5
0
0
0
0
= Unimplemented
4
3
PTA4
PTA3
Unaffected by reset
PTB4
PTB3
Unaffected by reset
0
0
0
DDRA4
0
DDRB4
0
0
0
DDRA3
0
DDRB3
0
0
0
0
2
PTA2
PTB2
PTC2
0
DDRA2
0
DDRB2
0
0
0
1
PTA1
PTB1
PTC1
0
DDRA1
0
DDRB1
0
DDRC1
0
Bit 0
PTA0
PTB0
PTC0
0
DDRA0
0
DDRB0
0
DDRC0
0
Figure 14-1. I/O Port Register Summary
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
133