MC68HC908LB8_05 Datasheet, PDF (107/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

HRP Registers
Address: HRPDCH — $0052 HRPDCL — $0053
Bit 15
14
13
12
Read: _DC10
DC9
DC8
DC7
Write:
Reset:
0
0
0
0
Bit 7
6
5
4
Read:
Write:
DC2
DC1
DC0
STEP4
Reset:
0
0
0
0
11
DC6
0
3
STEP3
0
10
DC5
0
2
STEP2
0
9
DC4
0
1
STEP1
0
Bit 8
DC3
0
Bit 0
STEP0
0
Figure 10-11. HRP Duty Cycle Registers (HRPDCH:HRPDCL)
DC[10:0] — 11-Bit Duty Cycle Value
STEP[4:0] — 5-Bit Dithering Step Value
10.8.3 HRP Period Registers
The two read/write period registers contain the 16-bit period of the PWM output after dithering. It is split
into two parts:
1. 11-bit period value (P[10:0]) used to generate the HRP’s output waveforms.
2. 5-bit step value (STEP[4:0]) the lower five bits of HRPPERH:HRPPERL, specifies how much time
is spent on the longer period (PERIOD2).
The output period including dithering in variable frequency mode is:
Output Period (seconds) = --P-----^[--1---0----:-0----^]-- + ---I--N-----T----^⎝⎛---S--------T-2------E--^S------^EP----L------^[[--²--4--^:---^{0-:----]0--------]}--^⎠⎞----
HRPCLK _{-------3---2--------- ¥ HRPCLK}
2^SEL[2:0]
where 2^SEL[2:0] is the STEP[4:0] scaling factor.
(EQ 10-12)
The output period in variable duty cycle mode does not include dithering. The period value is:
Period = ----P----[--1---0---:--0---]----
HRPCLK
(EQ 10-13)
Writes to the high byte (HRPPERH) are stored in a latch until the low byte (HRPPERL) is written. Both
registers are then updated simultaneously. This prevents glitches in the output period.
Address: HRPPERH — $0054 HRPPERL — $0055
Bit 15
14
13
12
11
10
9
Bit 8
Read: _P10
P9
P8
P7
P6
P5
P4
P3
Write:
Reset:
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Figure 10-12. HRP Period Registers (HRPPERH:HRPPERL)
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
107