MC68HC908LB8_05 Datasheet, PDF (120/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Low-Voltage Inhibit (LVI)
The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator.
Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor V_DD voltage. Clearing the LVI
reset disable bit, LVIRSTD, enables the LVI module to generate a reset when V_DD falls below a voltage,
V_TRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
Once an LVI reset occurs, the MCU remains in reset until V_DD rises above a voltage, V_TRIPR, which
causes the MCU to exit reset. See Chapter 17 System Integration Module (SIM) for the reset recovery
sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
12.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF level, software can monitor V_DD by polling
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be at 0 to enable the LVI module, and
the LVIRSTD bit must be at 1 to disable LVI resets.
12.3.2 Forced Reset Operation
In applications that require V_DD to remain above the V_TRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when V_DD falls below the V_TRIPF level. In the configuration register, the
LVIPWRD and LVIRSTD bits must be at 0 to enable the LVI module and to enable LVI resets.
12.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V_DD fall below V_TRIPF), the LVI will maintain a reset condition until
V_DD rises above the rising trip point voltage, V_TRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if V_DD is approximately equal to V_TRIPF. V_TRIPR is greater than
V_TRIPF by the hysteresis voltage, V_HYS.
MC68HC908LB8 Data Sheet, Rev. 1
120
Freescale Semiconductor