MC68HC908LB8_05 Datasheet, PDF (105/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

10.8 HRP Registers
The following registers control and monitor operation of the HRP:
• HRP control register (HRPCTRL)
• HRP duty cycle registers (HRPDCH: HRPDCL)
• HRP period registers (HRPPERH:HRPPERL)
• HRP deadtime register (HRPDT)
• HRP timebase registers (HRPTBH:HRPTBL)
HRP Registers
10.8.1 HRP Control Register
The HRPCTRL register does the following:
• Enables the HRP
• Controls the operating mode of the HRP
• Enables the SHTDWN, TOP, and BOT pins
• Enables interrupt functionality for the SHTDWN pin
Address: $0051
Bit 7
Read:
Write:
Reset:
6
5
SHTLVL HRPOE
0
0
= Unimplemented
4
SHTIF
0
3
SHTIE
0
2
SHTEN
0
1
HRP-
MODE
0
Figure 10-10. HRP Control Register (HRPCTRL)
Bit 0
HRPEN
0
SHTLVL — SHTDWN Pin Level
This read-only bit contains the current logic level of the SHTDWN pin. Reset clears the SHTLVL bit.
HRPOE — HRP Output Enable
This read/write bit enables/disables the TOP and BOT output pins.
1 = Pins PTB0/TOP and PTB1/BOT function as TOP and BOT outputs from the HRP module. The
contents of the port B data and data direction registers do not affect these pins.
0 = Pins PTB0/TOP and PTB1/BOT function as PTB0 and PTB1 general-purpose I/O pins. The
state of these pins is controlled by the port B data and data direction registers.
SHTIF — SHTDWN Interrupt Flag
This read/write bit is set when a falling edge or a low level is detected on the SHTDWN pin. Reset
clears the SHTIF bit. Writing 0 to SHTIF clears the bit.
1 = SHTDWN pin interrupt pending
0 = No SHTDWN pin interrupt pending
SHTIE — SHTDWN Interrupt Enable
This read/write bit enables HRP CPU interrupt service requests for the SHTDWN pin. Reset clears the
SHTIE bit.
1 = SHTDWN CPU interrupt requests enabled
0 = SHTDWN CPU interrupt requests disabled
SHTEN — Shutdown Pin Enable
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
105