MC68HC05V12 Datasheet, PDF (97/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
16-Bit Timer
Input Capture Register $14−$15
The free-running counter contents are transferred to the input capture
register on each proper signal transition regardless of whether the input
capture flag (ICF) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most
recent input capture.
After a read of the input capture register MSB ($14), the counter transfer
is inhibited until the LSB ($15) is also read. This characteristic causes
the time used in the input capture software routine and its interaction
with the main program to determine the minimum pulse period. A read
of the input capture register LSB ($15) does not inhibit the free-running
counter transfer since they occur on opposite edges of the internal bus
clock.
t_TLTL
t_TL
t_TH
TCAP
See control timing specifications for TCAP timing requirements.
Figure 9-2. TCAP Timing
NOTE:
The input capture pin (TCAP) and the output compare pin (TCMP) are
shared with PB7 and PB6 respectively. The timer’s TCAP input always
is connected to PB7. PB6 is the timer’s TCMP pin if the OCE bit in the
miscellaneous control register is set.
MC68HC05V12 — Rev. 2.0
16-Bit Timer
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Technical Data