MC68HC05V12 Datasheet, PDF (142/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital
14.5.1 Rx Digital Filter
The receiver section of the BDLC includes a digital low pass filter to
remove narrow noise pulses from the incoming message. An outline of
the digital filter is shown in Figure 14-5.
RX DATA
FROM
PHYSICAL
INTERFACE
(BDRxD)
INPUT
SYNC
DQ
4-BIT UP/DOWN COUNTER
UP/DOWN
OUT
DATA
LATCH
DQ
FILTERED
RX DATA OUT
MUX
INTERFACE
CLOCK
Figure 14-5. BDLC Rx Digital Filter Block Diagram
14.5.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see
f_BDLC parameter in Table 14-3). At each positive edge of the clock
signal, the current state of the receiver physical interface (BDRxD) signal
is sampled. The BDRxD signal state is used to determine whether the
counter should increment or decrement at the next negative edge of the
clock signal.
The counter will increment if the input data sample is high but decrement
if the input sample is low. Therefore, the counter will thus progress either
up toward 15 if, on average, the BDRxD signal remains high or progress
down toward 0 if, on average, the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter
decides that the condition of the BDRxD signal is at a stable logic level
1 and the data latch is set, causing the filtered Rx data signal to become
a logic level 1. Furthermore, the counter is prevented from overflowing
and can be decremented only from this state.
Technical Data
Byte Data Link Controller – Digital (BDLC–D)
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MC68HC05V12 — Rev. 2.0