MC68HC05V12 Datasheet, PDF (108/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being
transferred, a steady state low value is produced at the SCK pin of the
master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit is also used in conjunction with the clock phase control bit to
produce the desired clock-data relationship between master and
slave. See Figure 10-1.
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPOL bit can
be thought of as simply inserting an inverter in series with the SCK
line. The CPHA bit selects one of two fundamentally different clocking
protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.
As soon as SS goes low, the transaction begins and the first edge on
SCK invokes the first data sample. When CPHA = 1, SS may be
thought of as a simple output enable control. See Figure 10-1.
SPR1 and SPR0 — SPI Clock Rate Select Bits
These two bits select one of four baud rates (see Table 10-1) to be
used as SCK if the device is a master; however, they have no effect
in slave mode.
Table 10-1. Serial Peripheral Rate Selection
SPR1
0
0
1
1
SPR0
0
1
0
1
Internal MCU Clock
Divided by
2
4
16
32
Technical Data
Serial Peripheral Interface (SPI)
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MC68HC05V12 — Rev. 2.0