MC68HC05V12 Datasheet, PDF (155/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
BDLC MUX Interface
and arbitrate for the bus. If a CPU write to the BDR occurred after
104 • t_BDLC from the detection of the rising edge, then the BDLC will not
transmit, but will wait for the next IFS period to expire before attempting
to transmit the byte.
The variable pulse width modulation (VPW) symbols and J1850 bus
electrical characteristics are chosen carefully so that a logic 0 (active or
passive type) will always dominate over a logic 1 (active or passive type)
simultaneously transmitted. Hence, logic 0s are said to be dominant and
logic 1s are said to be recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted
a recessive bit, it loses arbitration and immediately stops transmitting.
This is known as bitwise arbitration.
Since a logic 0 dominates a logic 1, the message with the lowest value
will have the highest priority and will always win arbitration. For instance,
a message with priority 000 will win arbitration over a message with
priority 011.
This method of arbitration will work no matter how many bits of priority
encoding are contained in the message.
ACTIVE
TRANSMITTER A
PASSIVE
ACTIVE
TRANSMITTER B
PASSIVE
ACTIVE
J1850 BUS
PASSIVE
0
1
1
1
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
0
1
1
0
0
0
1
1
0
0
TRANSMITTER B WINS
ARBITRATION AND
CONTINUES
TRANSMITTING
DATA DATA DATA
DATA DATA
SOF
BIT 1 BIT 2 BIT 3
BIT 4 BIT 5
Figure 14-12. J1850 VPW Bitwise Arbitrations
MC68HC05V12 — Rev. 2.0
Byte Data Link Controller – Digital (BDLC–D)
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Technical Data