MC68HC05V12 Datasheet, PDF (72/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Resets
Freescale Semiconductor, Inc.
The recommended interactions and considerations for the COP
watchdog timer, STOP instruction, and WAIT instruction are
summarized in Table 5-1.
Table 5-1. COP Watchdog Timer Recommendations
IF These Conditions Exist:
STOP Instruction
WAIT Time
Converted to reset
WAIT time less than
COP timeout
Converted to reset
WAIT time MORE than
COP timeout
Acts as STOP
Any length WAIT time
THEN the COP Watchdog
Timer Should:
Enable or disable COP
Disable COP
Disable COP
5.4.2.5 COP Register
The COP register is shared with the most significant bit (MSB) of an
unimplemented user interrupt vector as shown in Figure 5-3. Reading
this location will return whatever user data has been programmed at this
location. Writing a 0 to the COPR bit in this location will clear the COP
watchdog timer.
Address:
Read:
Write:
Reset:
$3FF0
BIt 7
6
5
4
3
2
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
= Unimplemented
Figure 5-3. COP Watchdog Timer Location
Bit 0
X
COPR
X
Technical Data
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MC68HC05V12 — Rev. 2.0