MC68HC05V12 Datasheet, PDF (118/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Pulse Width Modulators (PWMs)
11.4.2 PWMB Control Register
Address: $0039
Bit 7
6
5
4
3
2
1
Read:
0
PSA1B PSA0B
Write:
0
PSB3B PSB2B PSB1B
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 11-6. PWMB Control Register (PWMBC)
Bit 0
PSB0B
0
PSA1B, PSA0B, and PSB3B−PSB0B — PWM Clock Rate Bits
These bits select the input clock rate for PWMB and determine the
period as shown in Table 11-2. These bits function exactly the same
as the corresponding bits in the PWMA control register except they
affect the PWMB output pin.
PSA1B–
PSA0B
00
01
10
11
Table 11-2. PWMB Clock Rates
PSB3B–
PSB0B
xxxx
0000–1111
0000–1111
0000–1111
RCLKB
SCLKB
PWMB OUT
Off
f_OP/1
f_OP/8
f_OP/16
Off
f_OP/1 – f_OP/16
f_OP/8 – f_OP/128
f_OP/16 – f_OP/256
Off
f_OP/64 – f_OP/1024
f_OP/512 – f_OP/8192
f_OP/1024 – f_OP/16384
NOTE:
Any non-zero value of PSA1B−PSA0B forces PB5 to the PWMB output
state. If PSA1B−PSA0B = 00, PB5 is determined by the port B data and
data direction registers as described in Section 7. Parallel
Input/Output (I/O).
Technical Data
Pulse Width Modulators (PWMs)
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MC68HC05V12 — Rev. 2.0