MC68HC05V12 Datasheet, PDF (19/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
List of Figures
Figure
Title
Page
13-1 A/D Status and Control Register (ADSCR) . . . . . . . . . . . . .130
13-2 A/D Data Register (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . .131
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
14-13
14-14
14-15
14-16
14-17
14-18
14-19
14-20
14-21
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
BDLC Input/Output (I/O) Register Summary . . . . . . . . . . . .137
BDLC Operating Modes State Diagram . . . . . . . . . . . . . . . .138
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . . .142
J1850 Bus Message Format (VPW) . . . . . . . . . . . . . . . . . . .144
J1850 VPW Symbols with Nominal Symbol Times . . . . . . .148
J1850 VPW Received Passive Symbol Times . . . . . . . . . . .151
J1850 VPW Received Passive
EOF and IFS Symbol Times . . . . . . . . . . . . . . . . . . . . . .152
J1850 VPW Received Active Symbol Times . . . . . . . . . . . .153
J1850 VPW Received BREAK Symbol Times . . . . . . . . . . .154
J1850 VPW Bitwise Arbitrations . . . . . . . . . . . . . . . . . . . . . .155
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . . .157
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
BDLC Analog and Roundtrip Delay Register (BARD) . . . . .163
BDLC Control Register 1 (BCR1) . . . . . . . . . . . . . . . . . . . . .165
BDLC Control Register 2 (BCR2) . . . . . . . . . . . . . . . . . . . . .167
Types of In-Frame Response (IFR) . . . . . . . . . . . . . . . . . . .171
BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . . .175
BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . . .177
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
Gauge Driver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .183
Full H-Bridge Coil Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Half H-Bridge Coil Driver . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Specification for Current Spikes . . . . . . . . . . . . . . . . . . . . . .186
Gauge Enable Register (GER) . . . . . . . . . . . . . . . . . . . . . . .188
Current Magnitude Registers . . . . . . . . . . . . . . . . . . . . . . . .189
MAJA Current Direction Register (DMAJA) . . . . . . . . . . . . .192
MAJB Current Direction Register (DMAJB) . . . . . . . . . . . . .192
MINA Current Direction Register (DMINA) . . . . . . . . . . . . . .193
MINB Current Direction Register (DMINB) . . . . . . . . . . . . . .193
MC68HC05V12 — Rev. 2.0
List of Figures
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Technical Data