MC68HC05V12 Datasheet, PDF (96/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

16-Bit Timer
Freescale Semiconductor, Inc.
The output compare register contents are continually compared with the
contents of the free-running counter. If a match is found, the
corresponding output compare flag (OCF) bit is set and the
corresponding output level (OLVL) bit is clocked to an output level
register. The output compare register values and the output level bit
should be changed after each successful comparison to establish a new
elapsed timeout. An interrupt can also accompany a successful output
compare provided the corresponding interrupt enable bit (OCIE) is set.
After a processor write cycle to the output compare register containing
the MSB ($16), the output compare function is inhibited until the LSB
($17) is also written. The user must write both bytes (locations) if the
MSB is written first. A write made only to the LSB ($17) will not inhibit the
compare function. The free-running counter is updated every four
internal bus clock cycles. The minimum time required to update the
output compare register is a function of the program rather than the
internal hardware.
The processor can write to either byte of the output compare register
without affecting the other byte. The output level (OLVL) bit is clocked to
the output level register regardless of whether the output compare flag
(OCF) is set or clear.
9.5 Input Capture Register $14−$15
Two 8-bit registers, which make up the 16-bit input capture register, are
read-only and are used to latch the value of the free-running counter
after the corresponding input capture edge detector senses a defined
transition. The level transition which triggers the counter transfer is
defined by the corresponding input edge bit (IEDG). Reset does not
affect the contents of the input capture register.
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter,
which is four internal bus clock cycles.
Technical Data
16-Bit Timer
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MC68HC05V12 — Rev. 2.0