MC68HC05V12 Datasheet, PDF (141/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
BDLC MUX Interface
14.4.1.7 Analog Loopback Mode
Analog loopback mode is used to determine if a bus fault has been
caused by a failure in the node’s off-chip analog transceiver or
elsewhere in the network. The BDLC analog loopback mode does not
modify the digital transmit or receive functions of the BDLC. It does,
however, ensure that once analog loopback mode is exited, the BDLC
will wait for an idle bus condition before participation in network
communication resumes. If the off-chip analog transceiver has a
loopback mode, it usually causes the input to the output drive stage to
be looped back into the receiver, allowing the node to receive messages
it has transmitted without driving the J1850 bus. In this mode, the output
to the J1850 bus typically is high impedance. This allows the
communication path through the analog transceiver to be tested without
interfering with network activity. Using the BDLC analog loopback mode
in conjunction with the analog transceiver’s loopback mode ensures
that, once the off-chip analog transceiver has exited loopback mode, the
BCLD will not begin communicating before a known condition exists on
the J1850 bus.
14.5 BDLC MUX Interface
The MUX interface is responsible for bit encoding/decoding and digital
noise filtering between the protocol handler and the physical interface.
TO CPU
MC68HC05V12 — Rev. 2.0
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 14-4. BDLC Block Diagram
Byte Data Link Controller – Digital (BDLC–D)
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Technical Data