MC68HC05V12 Datasheet, PDF (199/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Gauge Drivers
Coil Sequencer and Control
current scan cycle. Any time this bit is set and the SYNIE bit is set, a
CPU interrupt will be generated. The bit will be set even if minor D is
not enabled in the GER, since the scanning sequence time is not
affected by the enabling or disabling of the gauges. This bit will
function in either auto or manual mode and does not affect the
scanning operation in any way. It serves only as a status flag. Note
that once this bit is set, the software will have a time, 2 * t_GCS, to
update the CDR and CMR register if new data is to be used in the next
scan cycle.
The bit is cleared by writing a 1 to the SYNR bit and by reset.
SYNR — Synchronize Flag Reset Bit
This bit is used to clear the SYNF bit. Writing a 1 to this bit will clear
the SYNF bit if the SYNF bit was set during a read of the SSCR. This
bit will always read 0.
GCS1–GCS0 — Gauge Clock Select Bits
These bits determine the clock divide ratio for the clock used by the
scan sequencer. This provides for the use of several different system
clock rates while still providing the gauge driver module with the same
scanning rate.
Table 15-2. Gauge Module Clock Select Bits
CPU Bus
Clock Frequency
f_op = 0.5 MHz
f_op = 1.0 MHz
f_op = 2.0 MHz
f_op = 4.0 MHz⁽¹⁾
1. Must not be selected
GCS1
0
0
1
1
GCS0
0
1
0
1
Division
512
1024
2048
4096
Scan Cycle
Time
t_GCS
t_GCS
t_GCS
t_GCS
SCNS — Scan Start Bit
When the coil sequencer is being operated in manual mode, this bit is
used to initiate a scan cycle. Setting this bit starts the scan cycle. All
CMRs and CDRs will transfer data from the master to the slave when
this bit is set.
MC68HC05V12 — Rev. 2.0
Gauge Drivers
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Technical Data