MC68HC05V12 Datasheet, PDF (163/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
BDLC CPU Interface
14.7.1 BDLC Analog and Roundtrip Delay
This register programs the BDLC to compensate for various delays of
different external transceivers. The default delay value is 16 µs. Timing
adjustments from 9 µs to 24 µs in steps of 1 µs are available. The BARD
register can be written only once after each reset, after which they
become read-only bits. The register may be read at any time.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
ATE RXPOL
Write:
0
BO3
BO2
BO1
BO0
Reset: 1
1
0
0
0
1
1
1
= Unimplemented
Figure 14-16. BDLC Analog and Roundtrip
Delay Register (BARD)
ATE — Analog Transceiver Enable Bit
The analog transceiver enable (ATE) bit is used to select either the
on-board or an off-chip analog transceiver.
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
NOTE: This device does not contain an on-board transceiver. This bit should be
programmed to a logic 0 for proper operation.
RXPOL — Receive Pin Polarity Bit
The receive pin polarity (RXPOL) bit is used to select the polarity of
an incoming signal on the receive pin. Some external analog
transceivers invert the receive signal from the J1850 bus before
feeding it back to the digital receive pin.
1 = Select normal/true polarity; true non-inverted signal from the
J1850 bus; for example, the external transceiver does not
invert the receive signal
0 = Select inverted polarity, where an external transceiver inverts
the receive signal from the J1850 bus
MC68HC05V12 — Rev. 2.0
Byte Data Link Controller – Digital (BDLC–D)
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Technical Data