MC68HC05V12 Datasheet, PDF (132/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Analog-to-Digital (A/D) Converter
13.7 A/D during Wait Mode
The A/D converter continues normal operation during wait mode. To
decrease power consumption during wait mode, it is recommended that
both the ADON and ADRC bits in the A/D status and control registers be
cleared if the A/D converter is not being used. If the A/D converter is in
use and the system clock rate is above 1.0 MHz, it is recommended that
the ADRC bit be cleared.
NOTE: As the A/D converter continues to function normally in wait mode, the
COCO bit is not cleared.
13.8 A/D during Stop Mode
In stop mode, the comparator and charge pump are turned off and the
A/D ceases to function. Any pending conversion is aborted. When the
clocks begin oscillation upon leaving stop mode, a finite amount of time
passes before the A/D circuits stabilize enough to provide conversions
to the specified accuracy. Normally, the delays built into the device when
coming out of stop mode are sufficient for this purpose so that no explicit
delays need to be built into the software.
NOTE:
Although the comparator and charge pump are disabled in stop mode,
the A/D data and status/control registers are not modified. Disabling the
A/D prior to entering stop mode will not affect the stop mode current
consumption.
Technical Data
Analog-to-Digital (A/D) Converter
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MC68HC05V12 — Rev. 2.0