MC68HC05V12 Datasheet, PDF (168/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital
a minimum of inter-frame symbol time (t_TRV6) before message
transmission. See 17.12 BDLC Transmitter VPW Symbol
Timings (BARD) Bits BO[3:0] = 0111.
DLOOP — Digital Loopback Mode Bit
This bit determines the source to which the digital receive input
(BDRxD) is connected and can be used to isolate bus fault conditions
(see Figure 14-14). If a fault condition has been detected on the bus,
this control bit allows the programmer to connect the digital transmit
output to the digital receive input. In this configuration, data sent from
the transmit buffer will be reflected back into the receive buffer. If no
faults exist in the BDLC, the fault is in the physical interface block or
elsewhere on the J1850 bus.
1 = When set, BDRxD is connected to BDTxD. The BDLC is now
in digital loopback mode.
0 = When cleared, BDTxD is not connected to BDRxD. The BDLC
is taken out of digital loopback mode and can now drive or
receive the J1850 bus normally (given ALOOP is not set). After
writing DLOOP to 0, the BDLC requires the bus to be idle for a
minimum of end-of-frame symbol (t_tv4) time before allowing a
reception of a message. The BDLC requires the bus to be idle
for a minimum of inter-frame separator symbol (t_tv6) time
before allowing any message to be transmitted.
RX4XE — Receive 4X Enable Bit
This bit determines if the BDLC operates at normal transmit and
receive speed (10.4 kbps) or receive only at 41.6 kbps. This feature
is useful for fast downloading of data into a J1850 node for diagnostic
or factory programming of the node.
1 = When set, the BDLC is put in 4X receive-only operation.
0 = When cleared, the BDLC transmits and receives at 10.4 kbps.
Reception of a BREAK symbol automatically clears this bit and
sets BDLC state vector register (BSVR) to $001C.
Technical Data
Byte Data Link Controller – Digital (BDLC–D)
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MC68HC05V12 — Rev. 2.0