MC68HC05V12 Datasheet, PDF (68/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Resets
Freescale Semiconductor, Inc.
IRQ
RESET
OSC
DATA
ADDRESS
V_DD
V_DD
ADDRESS
STOPEN
(PULSE WIDTH = 3 x t_CYC)
D
LATCH
R
CLOCKED
PH2
ONE-SHOT
COP WATCHDOG
(COPR)
LOW-VOLTAGE
RESET (LVR)
POWER-ON RESET
(POR)
ILLEGAL ADDRESS
(ILADDR)
DISABLED STOP
INSTRUCTION
S
D
LATCH
PH2
Figure 5-1. Reset Block Diagram
TO IRQ
LOGIC
MODE
SELECT
CPU
TO OTHER
RST
PERIPHERALS
5.3 External Reset (RESET)
The RESET pin is the only external source of a reset. This pin is
connected to a Schmitt trigger input gate to provide an upper and lower
threshold voltage separated by a minimum amount of hysteresis. This
external reset occurs whenever the RESET pin is pulled below the lower
threshold and remains in reset until the RESET pin rises above the
upper threshold. This active low input will generate the RST signal and
reset the CPU and peripherals.
NOTE: Activation of the RST signal is generally referred to as reset of the
device, unless otherwise specified.
The RESET pin can also act as an open drain output. It will be pulled to
a low state by an internal pulldown that is activated by any reset source.
This reset pulldown device will be asserted only for three to four cycles
of the internal clock, f_OP, or as long as an internal reset source is
Technical Data
Resets
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MC68HC05V12 — Rev. 2.0