MC68HC05V12 Datasheet, PDF (69/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Resets
Internal Resets
asserted. When the external RESET pin is asserted, the pulldown device
will be turned on for only the three to four internal clock cycles.
5.4 Internal Resets
The five internally generated resets are:
• Initial power-on reset function
• Computer operating properly reset (COPR)
• Illegal address detector
• Low-voltage reset (LVR)
• Disabled STOP instruction
All internal resets will also assert (pull to logic 0) the external RESET pin
for the duration of the reset or three to four internal clock cycles,
whichever is longer.
5.4.1 Power-On Reset (POR)
The internal power-on reset (POR) is generated on power-up to allow
the clock oscillator to stabilize. The POR is strictly for power turn-on
conditions and is not able to detect a drop in the power supply voltage
(brown-out). There is an oscillator stabilization delay of 4064 internal
processor bus clock cycles (PH2) after the oscillator becomes active.
The POR will generate the RST signal which will reset the CPU. If any
other reset function is active at the end of this 4064-cycle delay, the RST
signal will remain in the reset condition until the other reset condition(s)
end.
POR will activate the RESET pin pulldown device connected to the pin.
V_DD must drop below V_POR for the internal POR circuit to detect the next
rise of V_DD.
MC68HC05V12 — Rev. 2.0
Resets
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Technical Data