MC68HC05V12 Datasheet, PDF (114/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Pulse Width Modulators (PWMs)
f_OP (CPU BUS CLOCK)
RCLK
SCLK
÷1, ÷8, ÷16
INTEGER DIVIDE
÷1–16
6-BIT COUNTER
(÷64)
MODULUS AND
COMPARATOR
PWM DATA
REGISTER
PWM DATA
BUFFER
PWMx
PIN LOGIC
PWMx
PWM CONTROL REGISTERS AND BUFFERS
Figure 11-1. PWM Block Diagram
11.3 PWM Functional Description
The PWM is capable of generating signals from 0 percent to 100 percent
duty cycle. A $00 in the PWM data register yields a low output (0
percent), but a $3F yields a duty of 63/64. To achieve the 100 percent
duty (high output), the polarity control bit is set to 0 while the data register
has $00 in it.
When not in use, the PWM system can be shut off to save power by
clearing the clock rate select bits PSA0x and PSA1x in PWM control
registers.
Writes to the PWM data registers are buffered and can, therefore, be
performed at any time without affecting the output signal. When the
PWM subsystem is enabled, a write to the PWM control register will
become effective immediately.
When the PWM subsystem is enabled, a write to the PWM data register
will not become effective until the end of the current PWM period has
Technical Data
Pulse Width Modulators (PWMs)
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MC68HC05V12 — Rev. 2.0