MC68HC05V12 Datasheet, PDF (87/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Technical Data — MC68HC05V12
Section 8. Core Timer
8.1 Contents
8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
8.3 Core Timer Status and Control Register. . . . . . . . . . . . . . . . . .89
8.4 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .91
8.5 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .92
8.6 Core Timer during Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . .92
8.2 Introduction
The core timer for this device is a 12-stage multi-functional ripple
counter. Features include:
• Timer overflow
• Power-on reset (POR)
• Real-time interrupt (RTI)
• Computer operating properly (COP) watchdog timer
As seen in Figure 8-1, the internal peripheral clock is divided by four
then drives an 8-bit ripple counter. The value of this 8-bit ripple counter
can be read by the CPU at any time by accessing the core timer counter
register (CTCR) at address $09. A timer overflow function is
implemented on the last stage of this counter, giving a possible interrupt
rate of the internal peripheral clock(E)/1024. This point is then followed
by two more stages, with the resulting clock (E/2048) driving the real-
time interrupt circuit (RTI).
The RTI circuit consists of three divider stages with a 1-of-4 selector.
The output of the RTI circuit is further divided by eight to drive the mask
MC68HC05V12 — Rev. 2.0
Core Timer
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Technical Data