MC68HC05V12 Datasheet, PDF (165/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
BDLC CPU Interface
14.7.2 BDLC Control Register 1
This register is used to configure and control the BDLC.
Address: $003A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
IMSG CLKS
R1
R0
IE
WCM
Write:
R
R
Reset: 1
1
1
0
0
0
0
0
R = Reserved
Figure 14-17. BDLC Control Register 1 (BCR1)
IMSG — Ignore Message Bit
This bit is used to disable the receiver until a new start-of-frame (SOF)
is detected.
1 = Disable receiver. When set, all BDLC interrupt requests will be
masked (except $20 in BSVR) and the status bits will be held
in their reset state. If this bit is set while the BDLC is receiving
a message, the rest of the incoming message will be ignored.
0 = Enable receiver. This bit is cleared automatically by the
reception of an SOF symbol or a BREAK symbol. It will then
generate interrupt requests and will allow changes of the
status register to occur. However, these interrupts may still be
masked by the interrupt enable (IE) bit.
CLKS — Clock Bit
For J1850 bus communications to take place, the nominal BDLC
operating frequency (f_BDLC) must always be 1.048576 MHz or 1 MHz.
The CLKS register bit allows the user to select the frequency
(1.048576 MHz or 1 MHz) used to automatically adjust symbol timing.
1 = Binary frequency (1.048576 MHz) selected for f_BDLC
0 = Integer frequency (1 MHz) selected for f_BDLC
R1 and R0 — Rate Select Bits
These bits determine the amount by which the frequency of the MCU
system clock is divided to form the MUX interface clock (f_BDLC) which
MC68HC05V12 — Rev. 2.0
Byte Data Link Controller – Digital (BDLC–D)
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Technical Data