MC68HC05V12 Datasheet, PDF (83/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
Port B
7.3.2 Port A Data Direction Register
Each port A I/O pin may be programmed as an input by clearing the
corresponding bit in the DDRA or programmed as an output by setting
the corresponding bit in the DDRA. The DDRA can be accessed at
address $0004 and is cleared by reset.
7.4 Port B
Port B is an 8-bit bidirectional port. Each port B pin is controlled by the
corresponding bits in a data direction register and a data register as
shown in Figure 7-2. PB5 and PB4 are shared with the PWMs as shown
in Section 11. Pulse Width Modulators (PWMs) and PB7 and PB6 are
shared with 16-bit timer functions. See Section 9. 16-Bit Timer for timer
description. PB0-PB3 are shared with the SPI as shown in Section 10.
Serial Peripheral Interface (SPI). The port B data register is located at
address $0001. The port B data direction register (DDRB) is located at
address $0005. Reset clears the DDRB register. The port B data register
is unaffected by reset.
READ $0005
WRITE $0005
WRITE $0001
READ $0001
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
16-BIT TIMER,
PMWs, AND
SPI MUX LOGIC
I/O
OUTPUT
PIN
INTERNAL HC05
DATA BUS
RESET
(RST)
Figure 7-2. Port B I/O Circuitry
MC68HC05V12 — Rev. 2.0
Parallel Input/Output (I/O)
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Technical Data