MC68HC05V12 Datasheet, PDF (95/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
16-Bit Timer
Output Compare Register $16−$17
first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19,
$1B) is transferred to a buffer. This buffer value remains fixed after the
first MSB read, even if the user reads the MSB several times. This buffer
is accessed when reading the free-running counter or counter alternate
register LSB ($19 or $1B) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter
alternate register, if the MSB is read, the LSB also must be read to
complete the sequence.
The counter alternate register differs from the counter register in one
respect: A read of the counter register MSB can clear the timer overflow
flag (TOF). Therefore, the counter alternate register can be read at any
time without the possibility of missing timer overflow interrupts due to
clearing of the TOF.
The free-running counter is configured to $FFFC during reset and is a
read-only register only when the timer is enabled. During a power-on
reset, the counter also is preset to $FFFC and begins running only after
the TON bit in the timer control register is set. Because the free-running
counter is 16 bits preceded by a fixed divided-by-four prescaler, the
value in the free-running counter repeats every 262,144 internal bus
clock cycles. When the counter rolls over from $FFFF to $0000, the TOF
bit is set. When counter roll-over occurs, an interrupt also can be
enabled by setting its interrupt enable bit (TOIE).
NOTE:
To ensure that an interrupt does not occur, the I bit in the CCR should
be set while manipulating both the high and low byte registers of a
specific timer function.
9.4 Output Compare Register $16−$17
The 16-bit output compare register is made up of two 8-bit registers at
locations $16 (MSB) and $17 (LSB). The output compare register is
used for several purposes, such as indicating when a period of time has
elapsed. All bits are readable and writable and are not altered by the
timer hardware or reset. If the compare function is not needed, the two
bytes of the output compare register can be used as storage locations.
MC68HC05V12 — Rev. 2.0
16-Bit Timer
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Technical Data