MC68HC05V12 Datasheet, PDF (129/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Analog-to-Digital (A/D) Converter
Digital Section
13.4 Digital Section
This subsection describes the digital section.
13.4.1 Conversion Times
Each channel of conversion takes 32 clock cycles, which must be at a
frequency equal to or greater than 1 MHz.
13.4.2 Internal and Master Oscillators
If the MCU bus (f_OP) frequency is less than 1.0 MHz, an internal RC
oscillator (nominally 1.5 MHz) must be used for the A/D conversion
clock. This selection is made by setting the ADRC bit in the A/D status
and control registers to 1. In stop mode, the internal RC oscillator is
turned off automatically, although the A/D subsystem remains enabled
(ADON remains set). In wait mode, the A/D subsystem remains
functional. See 13.7 A/D during Wait Mode.
When the internal RC oscillator is being used as the conversion clock,
three limitations apply:
1. The conversion complete flag (COCO) must be used to determine
when a conversion sequence has been completed, due to the
frequency tolerance of the RC oscillator and its asynchronism with
regard to the MCU bus clock.
2. The conversion process runs at the nominal 1.5 MHz rate, but the
conversion results must be transferred to the MCU result registers
synchronously with the MCU bus clock so conversion time is
limited to a maximum of one channel per bus cycle.
3. If the system clock is running faster than the RC oscillator, the RC
oscillator should be turned off and the system clock used as the
conversion clock.
13.4.3 Multi-Channel Operation
A multiplexer allows the A/D converter to select one of five external
analog signals and four internal reference sources.
MC68HC05V12 — Rev. 2.0
Analog-to-Digital (A/D) Converter
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Technical Data