MC68HC05V12 Datasheet, PDF (157/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
BDLC Protocol Handler
14.6.1 Protocol Architecture
The protocol handler contains the state machine, Rx shadow register, Tx
shadow register, Rx shift register, Tx shift register, and loopback
multiplexer as shown in Figure 14-14.
BDRxD
TO PHYSICAL INTERFACE
BDTxD
DLOOP FROM BCR2
LOOPBACK CONTROL
LOOPBACK
MULTIPLEXER
STATE MACHINE
Rx SHIFT REGISTER
Rx SHADOW REGISTER
8
Tx SHIFT REGISTER
Tx SHADOW REGISTER
8
TO CPU INTERFACE AND Rx/Tx BUFFERS
Figure 14-14. BDLC Protocol Handler Outline
MC68HC05V12 — Rev. 2.0
Byte Data Link Controller – Digital (BDLC–D)
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Technical Data