MC68HC05V12 Datasheet, PDF (117/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Pulse Width Modulators (PWMs)
PWM Registers
11.4.1 PWMA Control Register
Address: $0037
Bit 7
6
5
4
3
2
1
Read:
0
PSA1A PSA0A
Write:
0
PSB3A PSB2A PSB1A
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 11-5. PWMA Control Register (PWMAC)
Bit 0
PSB0A
0
PSA1A, PSA0A, PSB3A−PSB0A — PWMA Clock Rate Bits
These bits select the input clock rate and determine the period as
shown in Table 11-1. Note that some output frequencies can be
obtained with more than one combination of PSA and PSB values.
For instance, a PWMA output of f_OP/512 can be obtained with either
PSA−PSA0 = 10 and PSB3−PSB0 = $0 or PSA1−PSA0 = 01 and
PSB3−PSB0 = $07. The frequency division provided by the PSB
values will be one more that the value written to the register. For
example, a $0 written to the PSB bits provides a ÷1 and a $1 provides
a ÷2, etc.
This scheme allows for 38 unique frequency selections.
NOTE:
Any non-zero value of PSA1A−PSA0A forces PB4 to the PWMA output
state. If PSA1A:PSA0A = 00, PB4 is determined by the port B data and
data direction registers as described in Section 7. Parallel
Input/Output (I/O).
PSA1A–
PSA0A
00
01
10
11
Table 11-1. PWMA Clock Rates
PSB3A–
PSB0A
xxxx
0000–1111
0000–1111
0000–1111
RCLKA
SCLKA
Off
f_OP/1
f_OP/8
f_OP/16
Off
f_OP/1 – f_OP/16
f_OP/8 – f_OP/128
f_OP/16 – f_OP/256
PWMA Out
Off
f_OP/64 – f_OP/1024
f_OP/512 – f_OP/8192
f_OP/1024 – f_OP/16384
MC68HC05V12 — Rev. 2.0
Pulse Width Modulators (PWMs)
For More Information On This Product,
Go to: www.freescale.com
Technical Data