MC68HC05V12 Datasheet, PDF (175/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
BDLC CPU Interface
14.7.4 BDLC State Vector Register
This register is provided to substantially decrease the CPU overhead
associated with servicing interrupts while under operation of a multiplex
protocol. It provides an index offset that is directly related to the BDLC’s
current state, which can be used with a user-supplied jump table to
rapidly enter an interrupt service routine. This eliminates the need for the
user to maintain a duplicate state machine in software.
Address: $003C
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
I3
I2
I1
I0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-20. BDLC State Vector Register (BSVR)
I0, I1, I2, and I3 — Interrupt Source Bits
These bits indicate the source of the interrupt request that currently is
pending. The encoding of these bits are listed in Table 14-5.
Table 14-5. BDLC Interrupt Sources
BSVR I3 I2 I1 I0
$00 0 0 0 0
$04 0 0 0 1
$08 0 0 1 0
$0C 0 0 1 1
$10 0 1 0 0
$14 0 1 0 1
$18 0 1 1 0
$1C 0 1 1 1
$20 1 0 0 0
Interrupt Source
No interrupts pending
Received EOF
Received IFR byte (RXIFR)
BDLC Rx data register full (RDRF)
BDLC Tx data register empty (TDRE)
Loss of arbitration
Cyclical redundancy check (CRC) error
Symbol invalid or out of range
Wakeup
Priority
0 (Lowest)
1
2
3
4
5
6
7
8 (Highest)
MC68HC05V12 — Rev. 2.0
Byte Data Link Controller – Digital (BDLC–D)
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Technical Data