MC68HC05V12 Datasheet, PDF (148/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital
ACTIVE
PASSIVE
ACTIVE
PASSIVE
128 µs
OR
(A) LOGIC 0
128 µs
OR
(B) LOGIC 1
64 µs
64 µs
ACTIVE
PASSIVE
ACTIVE
PASSIVE
≥ 240 µs
(C) BREAK
200 µs
(D) START OF FRAME
200 µs
(E) END OF DATA
280 µs
300 µs
20 µs
IDLE > 300 µs
(F) END OF FRAME
(G) INTER-FRAME
SEPARATION
(H) IDLE
Figure 14-7. J1850 VPW Symbols with Nominal Symbol Times
Logic 1
A logic 1 is defined as either:
– An active-to-passive transition followed by a passive period
128 µs in length, or
– A passive-to-active transition followed by an active period
64 µs in length
See Figure 14-7(b).
Technical Data
Byte Data Link Controller – Digital (BDLC–D)
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MC68HC05V12 — Rev. 2.0