MC68HC05V12 Datasheet, PDF (84/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
7.4.1 Port B Data Register
Each port B I/O pin has a corresponding bit in the port B data register.
When a port B pin is programmed as an output, the state of the
corresponding data register bit determines the state of the output pin.
When a port B pin is programmed as an input, any read of the port B data
register will return the logic state of the corresponding I/O pin. The port
B data register is unaffected by reset.
7.4.2 Port B Data Direction Register
Each port B I/O pin may be programmed as an input by clearing the
corresponding bit in the DDRB or programmed as an output by setting
the corresponding bit in the DDRB. The DDRB can be accessed at
address $0005. The DDRB is cleared by reset.
7.5 Port C
Port C is an 8-bit bidirectional port shared with the IRQ interrupt
subsystem as shown in Figure 7-3. Each pin is controlled by the
corresponding bits in a data direction register and a data register. The
port C data register is located at address $0002. The port C data
direction register (DDRC) is located at address $0006. Reset clears
DDRC. The port C data register is unaffected by reset.
READ $0006
WRITE $0006
WRITE $0002
RREAD $0002
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
I/O
OUTPUT
PIN
INTERNAL HC05
DATA BUS
RESET
(RST)
TO IRQ SUBSYSTEM
SEE FIGURE 4-2.
Figure 7-3. Port C I/O Circuitry
Technical Data
Parallel Input/Output (I/O)
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MC68HC05V12 — Rev. 2.0