MC68HC05V12 Datasheet, PDF (21/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Technical Data — MC68HC05V12
List of Tables
Table
Title
Page
4-1 Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . . .57
5-1 COP Watchdog Timer Recommendations . . . . . . . . . . . . . . . .72
8-1 RTI and COP Rates at 2.1 MHz . . . . . . . . . . . . . . . . . . . . . . . .90
10-1 Serial Peripheral Rate Selection. . . . . . . . . . . . . . . . . . . . . . .108
11-1 PWMA Clock Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
11-2 PWMB Clock Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
12-1 Erase Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
12-2 EEPROM Write/Erase Cycle Reduction . . . . . . . . . . . . . . . . .124
13-1 A/D Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .131
14-1
14-2
14-3
14-4
14-5
BDLC J1850 Bus Error Summary. . . . . . . . . . . . . . . . . . . . . .161
BDLC Transceiver Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
BDLC Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
BDLC Transmit In-Frame Response
Control Bit Priority Encoding . . . . . . . . . . . . . . . . . . . . . . .170
BDLC Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
15-1 Coil Scanning Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
15-2 Gauge Module Clock Select Bits . . . . . . . . . . . . . . . . . . . . . .199
16-1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . .212
16-2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .213
16-3 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .215
MC68HC05V12 — Rev. 2.0
List of Tables
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Technical Data