MC68HC05V12 Datasheet, PDF (56/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Interrupts
Freescale Semiconductor, Inc.
4.2 Introduction
The MCU can be interrupted eight different ways:
1. Non-maskable software interrupt instruction (SWI)
2. External asynchronous interrupt (IRQ)
3. External interrupt via IRQ on port C bits PC0–PC7 (IRQ)
4. Internal 16-bit timer interrupt (TIMER)
5. Internal BDLC interrupt (BDLC)
6. Internal serial peripheral interface interrupt (SPI)
7. Internal 8-bit timer interrupt (CTIMER)
8. Internal gauge interrupt (GAUGE)
4.3 CPU Interrupt Processing
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
reset, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is
complete.
If interrupts are not masked (I bit in the condition code register (CCR) is
clear) and the corresponding interrupt enable bit is set, then the
processor will proceed with interrupt processing. Otherwise, the next
instruction is fetched and executed. If an interrupt occurs, the processor
completes the current instruction, then stacks the current central
processor unit (CPU) register states, sets the I bit to inhibit further
interrupts, and finally checks the pending hardware interrupts. If more
than one interrupt is pending after the stacking operation, the interrupt
with the highest vector location shown in Table 4-1 will be serviced first.
The SWI is executed the same as any other instruction, regardless of the
I-bit state.
Technical Data
Interrupts
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MC68HC05V12 — Rev. 2.0