MC68HC05V12 Datasheet, PDF (100/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

16-Bit Timer
Freescale Semiconductor, Inc.
Accessing the timer status register satisfies the first condition required
to clear status bits. The remaining step is to access the register
corresponding to the status bit.
A problem can occur when using the timer overflow function and reading
the free-running counter at random times to measure an elapsed time.
Without incorporating the proper precautions into software, the timer
overflow flag could unintentionally be cleared if both of these occur:
1. The timer status register is read or written when TOF is set.
2. The MSB of the free-running counter is read but not for the
purpose of servicing the flag.
The counter alternate register at address $1A and $1B contains the
same value as the free-running counter (at address $18 and $19);
therefore, this alternate register can be read at any time without affecting
the timer overflow flag in the timer status register.
9.8 16-Bit Timer during Wait Mode
The CPU clock halts during wait mode, but the timer remains active if
turned on prior to entering wait mode. If interrupts are enabled, a timer
interrupt will cause the processor to exit wait mode.
9.9 16-Bit Timer during Stop Mode
In stop mode, the timer stops counting and holds the last count value if
stop mode is exited by an interrupt. If reset is used, the counter is forced
to $FFFC. During STOP, if the timer is on and at least one valid input
capture edge occurs at the TCAP pin, the input capture detect circuit is
armed. This does not set any timer flags or wake up the MCU, but when
the MCU does wake up, there is an active input capture flag and data
from the first valid edge that occurred during stop mode. If reset is used
to exit stop mode, then no input capture flag or data remains, even if a
valid input capture edge occurred.
Technical Data
16-Bit Timer
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MC68HC05V12 — Rev. 2.0