MC68HC05V12 Datasheet, PDF (64/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Interrupts
Freescale Semiconductor, Inc.
are all cleared. The IRQA is useful for cancelling unwanted or
spurious interrupts which may have occurred while servicing the initial
IRQ interrupt.
NOTE:
The IRQ flag is cleared automatically during the IRQ vector fetch. The
IRQPC latch is not cleared automatically (to permit interrupt source
differentiation as long as the Interrupt source is present) and must be
cleared from within the IRQ service routine.
4.7.2 External Interrupt Timing
If the interrupt mask bit (I bit) of the condition code register (CCR) is set,
all maskable interrupts (internal and external) are disabled. Clearing the
I bit enables interrupts. The interrupt request is latched immediately
following the falling edge of the IRQ source. It is then synchronized
internally and serviced as specified by the contents of $3FFA and
$3FFB. The IRQ timing diagram is shown in Figure 4-4.
IRQ
IRQ1 (PORT)
.
.
.
IRQn (PORT)
t_ILIH
t_ILIL
t_ILIH
IRQ
(MCU)
Figure 4-4. External Interrupts Timing Diagram
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-
only trigger is available as a mask option for the IRQ pin only.
Technical Data
Interrupts
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MC68HC05V12 — Rev. 2.0