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MC68HC05V12 Datasheet, PDF (237/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit
Freescale Semiconductor, Inc.
Electrical Specifications
BDLC Transmitter VPW Symbol Timings (BARD) Bits BO[3:0] = 0111
17.12 BDLC Transmitter VPW Symbol Timings (BARD) Bits BO[3:0] = 0111
Characteristic(1)
Passive logic 0
Passive logic 1
Active logic 0
Active logic 1
Start of frame (SOF)
End of data (EOD)
End of frame (EOF)
Inter-frame separator (IFS)
1. fBDLC = 1.048576 MHz or 1.0 MHz
Number Symbol Min
10
tTVP1
62
11
tTVP2
126
12
tTVA1
126
13
tTVA2
62
14
tTVA3
198
15
tTVP3
198
16
tTV4
278
17
tTV6
298
Typ Max
64
66
128 130
128 130
64
66
200 202
200 202
280 282
300 302
Unit
µs
µs
µs
µs
µs
µs
µs
µs
17.13 BDLC Receiver VPW Symbol Timings (BARD) Bits BO[3:0] = 0111
Characteristic(1)
Passive logic 0
Passive logic 1
Active logic 0
Active logic 1
Start of frame (SOF)
End of data (EOD)
End of Frame (EOF)
Break
1. fBDLC = 1.048576 MHz or 1.0 MHz
Number Symbol Min
10
tTRVP1
34
11
tTRVP2
96
12
tTRVA1
96
13
tTRVA2
34
14
tTRVA3
163
15
tTRVP3
163
16
tTRV4
239
18
tTRV6
239
Typ Max
64
96
128 163
128 163
64
96
200 239
200 239
280 320
—
—
Unit
µs
µs
µs
µs
µs
µs
µs
µs
NOTE: The receiver symbol timing boundaries are subject to an uncertainty of
1 tBDLC µs due to sampling considerations.
MC68HC05V12 — Rev. 2.0
Electrical Specifications
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Technical Data